This invention relates to computer structures which employ scan techniques for internal diagnostics and system initialization. More particularly, the invention can be applied to electronic circuits in self-testing computers which employ a double-latch technique for implementing level sensitive scan design (LSSD). Other applications of the invention are also contemplated, such as single-latch or edge-triggered logic designs.
The level sensitive scan design method of IBM Corporation is one of the better known methods for internal scan path testing of LSI logic circuits employed in several classes of computer systems. Specifically, level sensitive scan design is a logic design scheme relying on achievement of a preselected voltage level for logic values, as opposed to edges of a signal in a digital data stream. Further, the logic circuit in an LSI circuit component is divided into combinatorial circuit portions and sequential circuit portions. The sequential circuits can be connected in series through switching circuits, which when connected comprise a shift register.
The testing of an LSSD circuit or other scan testable circuits is performed by switching between a "shift mode" and a "normal mode." In the shift mode, a scan signal is input to the shift register whereby data is applied in a predetermined pattern of ones and zeroes. The sequential circuits are then disconnected by the switches and returned to the logic circuit. A predetermined logic operation is then performed, after which the sequential circuits are reconnected to form the shift register, and the data of the shift register is read out and checked.
Scan testable circuits have certain disadvantages. For example, extra signal lines are required to implement the test function. A circuit using a double-latch technique to implement level sensitive scan design (LSSD) requires two scan clocks and a scan mode enable signal in addition to the conventional system clocks. In the past, separate lines had been required for conveying these signals across the backplane bus of a computer system among the various circuit cards. As a consequence, there has been an allocation of a certain number of pins for circuits and signal traces for carrying signals. It is desirable to minimize the number of pins and signal traces required for an LSSD circuit employing a double-latch technique.